代PO, 勿站內信!! <工作地點> 台北市11052信義路四段460號12樓 履歷請寄：Jackie Su ([email protected]) <薪資福利> 薪資: 16~20萬*12個月+ESPP+分紅 (月薪視個人能力調整) 分紅：視個人績效與公司營運 特休假：到職第一年12天, 之後逐年累加1天, 彈休另計 全薪病假：10天 另有生日假1天, 公益假5天, 緊急事假4周(皆為全薪) <職缺> ○ Senior ASIC designer < Experience Required > ‧ 5 - 10 years in ASIC experience. Network ASIC experience is a plus. ‧ Strong tracking record of ASIC design from concept to mass production ‧ Hands-on experience on Verilog HDL coding. ‧ Experience of high performance ASIC design flow from specification to system bringing up ‧ Highly motivated, positive, detail oriented and responsible ‧ Good team player and good communication skills ‧ MSEE/MSCS ○ Senior ASIC verification < Experience Required > ‧ 5 - 10 years in ASIC design verification. ‧ Hands-on experience on Verilog HDL verification ‧ Experience of high performance ASIC design flow from specification to system bringing up ‧ Knowledge of System Verilog and UVM verification methodology ‧ Highly motivated, positive, detail oriented and responsible ‧ Good team player and good communication skills ‧ MSEE/MSCS -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 59.124.228.78 (臺灣) ※ 文章網址: https://webptt.cc/bbs/Tech_Job/M.1599196501.A.320.html