Job Description 1 IC package substrate design and layout 1.1 Package type includes flip-chip and wirebond. Single die design and multi -die design 1.2 Substrate layer count from 2 layers to 20+ layers. Preferred experience is at least 4 layers (1-2-1) 1.3 "High-speed (DDR, SerDes, PCIe...) signal routing optimization" 1.4 Good knowledge in substrate layout design rules and package assembly desig n rules 2 Chip-Package-PCB co-design 2.1 Review die bump assignment and BGA ball assignment to provide suggestions to optimize the design 3 Other assignments and tasks 3.1 Project management 3.2 Operation assistance Requirements: 1 "Enthusiastic, proactive, and responsible. Has integrity" 2 At least 3-year working experience on IC package substrate layout 3 Hands-on experience using Cadence Allegro Package Designer (APD) 4 A bachelor degree or above in science or engineering is preferred. Outstandi ng candidate without a college degree will be considered Company Offers 1 Competitive salary and bonus 2 Unlimited career growth opportunity in company 3 Annual vacation allowance Working Hours: Monday - Friday. 8:30AM - 17:30PM with 15 minutes flexibility "Working Location: Jingmei, Taipei" Monthly salary: NTD50K - NTD100K Please send your resume directly to: [email protected] Company website: sarcinatech.com -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 114.136.41.187 ※ 文章網址: https://webptt.cc/bbs/Tech_Job/M.1555742271.A.73B.html