Job Description 1 Chip-Package-PCB channel simulation to validate package design 1.1 Package/PCB model extraction 1.2 Power integrity (PI) channel simulation for core power 1.3 Signal integrity (SI) and PI channel simulation for high speed interfaces such as DDR, SerDes, PCIe et al. 2 Package/PCB layout review and co-design 2.1 Package/PCB layout review 2.2 Provide design guidelines for PI/SI optimization 3 Other assignments and tasks 3.1 Project management 3.2 Operation assistance Requirements: 1 Enthusiastic, proactive, responsible, and has integrity 2 A Bachelor degree or a Master degree in Electrical Engineering 3 At least one year working experience on SI/PI simulation 4 Used SIWave and HFSS before. Familarity with Cadence APD is a plus Company Offers 1 Competitive salary and bonus 2 Solid training 3 Restrict-less career opportunity in company 4 Annual vacation allowance Working Hours: Monday - Friday. 8:30AM - 17:30PM with 15 minutes flexibility Working Location: Jingmei, Taipei Montly salary: NTD55K - NTD90K Please send your resume to: [email protected] Company website: http://www.sarcinatech.com/ -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 223.136.26.106 ※ 文章網址: https://webptt.cc/bbs/Tech_Job/M.1547128320.A.479.html